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rev. d - 15 january, 2001 1 ts80c51u2 ts83c51u2 ts87c51u2 double uart 8-bit cmos microcontroller 1. description ts80c51u2 is high performance cmos rom, otp and eprom versions of the 80c51 cmos single chip 8-bit microcontroller. the ts80c51u2 retains all features of the 80c51 with extended rom/eprom capacity (16 kbytes), 256 bytes of internal ram, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. in addition, the ts80c51u2 has a second uart, enhanced functions on both uart, enhanced timer 2, a hardware watchdog timer, a dual data pointer, a baud rate generator and a x2 speed improvement mechanism. the fully static design of the ts80c51u2 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the ts80c51u2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the timers, the serial port and the interrupt system are still operating. in the power-down mode the ram is saved and all other functions are inoperative. 2. features l 80c52 compatible 8051 pin and instruction compatible four 8-bit i/o ports three 16-bit timer/counters 256 bytes scratchpad ram l high-speed architecture 40 mhz @ 5v, 30mhz @ 3v x2 speed improvement capability (6 clocks/ machine cycle) 30 mhz @ 5v, 20 mhz @ 3v (equivalent to 60 mhz @ 5v, 40 mhz @ 3v) l second uart l baud rate generator l dual data pointer l on-chip rom/eprom (16k-bytes) l programmable clock out and up/down timer/ counter 2 l hardware watchdog timer (one-time enabled with reset-out) l asynchronous port reset l interrupt structure with 7 interrupt sources 4 level priority interrupt system l full duplex enhanced uarts framing error detection automatic address recognition l low emi (inhibit ale) l power control modes idle mode power-down mode power-off flag l once mode (on-chip emulation) l power supply: 4.5-5.5v, 2.7-5.5v l temperature ranges: commercial (0 to 70 o c) and industrial (-40 to 85 o c) l packages: pdil40, plcc44, vqfp44 1.4, cqpj44 (window), cdil40 (window) 3. the second uart in this document, uart_0 will make reference to the first uart (present in all atmel wireless & microcontrollers c51 derivatives) and uart_1 will make reference to the second uart, only present in the ts80c51u2 part. the second uart (uart_1) can be seen as an alternate function of port 1 (p1.2 or p1.6 for rxd1 and p1.3 or p1.7 for txd1) or can be connected to (pin6 or pin12) and (pin28 or pin34) of 44-pin package (see pin
2 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 configuration). uart_1 is fully compliant with the first one allowing an internal baud rate generator to be the clock source. this common internal baud rate generator can be used independently by each uart or both as clock source allowing to program various speeds. the ts80c51u2 provides 7 sources of interrupt with four priority levels. uart_1 has a lower priority than timer 2. the serial ports are full duplex meaning they can transmit and receive simultaneously. they are also receive buffered, meaning they can start reception of a second byte before a previously received byte has been read from the receive register. the serial port receive and transmit registers of uart_1 are both accessed at special function register sbuf_1. writing to sbuf_1 loads the transmit register and reading sbuf_1 accesses a physical separate receive register. the uart_1 port control and status is the special function register scon_1. this register contains not only the mode selection bit but also the 9th bit for transmit and receive (tb8_1 and rb8_1) and the serial port interrupt bits (ti_1 and ri_1). the automatic address recognition feature is enabled when multiprocessor communication is enabled. implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine address of each incoming frame and provides filtering capability. the uart_1 also comes with frame error detection, similar to the uart_0.
rev. d - 15 january, 2001 3 ts80c51u2 ts83c51u2 ts87c51u2 4. block diagram table 1. memory size pdil40 plcc44 vqfp44 1.4 rom (bytes) eprom (bytes) ts80c51u2 00 ts83c51u2 16k 0 ts87c51u2 0 16k timer 0 int ram 256x8 t0 t1 rxd txd wr rd ea/v pp psen ale/ xtal2 xtal1 uart_0 cpu timer 1 int1 ctrl int0 (2) (2) c51 core (2) (2) (2) (2) port 0 p0 port 1 port 2 port 3 parallel i/o ports p1 p2 p3 ib-bus reset prog watchdog vss vcc (2) (2) (1): alternate function of port 1 timer2 t2ex t2 (1) (1) (2): alternate function of port 3 rom /eprom 16kx8 rxd1 txd1 (3) (3) uart_1 (3): see pin description
4 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 5. sfr mapping the special function registers (sfrs) of the ts80c51u2 fall into the following categories: c51 core registers: acc, b, dph, dpl, psw, sp, auxr1 i/o port registers: p0, p1, p2, p3 timer registers: t2con, t2mod, tcon, th0, th1, th2, tmod, tl0, tl1, tl2, rcap2l, rcap2h serial i/o port registers for uart_0: saddr_0, saden_0, sbuf_0, scon_0 serial i/o port registers for uart_1: saddr_1, saden_1, sbuf_1, scon_1 baud rate generator registers: brl, bdrcon, bdrcon_1 power and clock control registers: pcon hdw watchdog timer reset: wdtrst, wdtprg interrupt system registers: ie, ip, iph others: auxr, ckcon table 2. all sfrs with their address and their reset value bit address- able non bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ffh f0h b 0000 0000 f7h e8h efh e0h acc 0000 0000 e7h d8h dfh d0h psw 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h scon_1 0000 0000 sbuf_1 xxxx xxxx c7h b8h ip x000 0000 saden_0 0000 0000 saden_1 0000 0000 bfh b0h p3 1111 1111 iph x000 0000 b7h a8h ie 0x00 0000 saddr_0 0000 0000 saddr_1 0000 0000 afh a0h p2 1111 1111 auxr1 xxxx xxx0 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon_0 0000 0000 sbuf_0 xxxx xxxx brl 0000 0000 bdrcon 0xxx 0000 bdrcon_1 0x00 00xx 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 00xx xxx0 ckcon xxxx xxx0 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved
rev. d - 15 january, 2001 5 ts80c51u2 ts83c51u2 ts87c51u2 6. pin configuration s 5 4 3 2 1 6 44 43 42 41 40 p1.4 p1.0/t2 p1.1/t2ex p1.3/txd_1 p1.2/rxd_1 vss1/nic* vcc p0.0/ad0 p0.2/ad2 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea/vpp txd_1 p2.7/a15 p2.5/a13 p2.6/a14 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 43 42 41 40 39 44 38 37 36 35 34 p1.4 p1.0/t2 p1.1/t2ex p1.3/txd_1 p1.2/rxd_1 vss1/nic* vcc p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea/vpp txd_1 p2.7/a15 p2.5/a13 p2.6/a14 p1.5 p1.6/rxd_1 p1.7/txd_1 rst p3.0/rxd_0 rxd_1 p3.1/txd_0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5 p1.6/rxd_1 p1.7/txd_1 rst p3.0/rxd_0 rxd_1 p3.1/txd_0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p0.3/ad3 nic* nic* *nic: no internal connection 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 plcc/cqpj 44 33 32 31 30 29 28 27 26 25 24 23 vqfp44 1.4 1 2 3 4 5 6 7 8 9 10 11 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22 p1.7/txd_1 rst p3.0/rxd_0 p3.1/txd_0 p1.3/txd_1 1 p1.5 p3.2/int0 p3.3/int1 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0 / a8 p2.1 / a9 p2.2 / a10 p2.3 / a11 p2.4 / a12 p0.4 / a4 p0.6 / a6 p0.5 / a5 p0.7 / a7 ale/prog psen ea/vpp p2.7 / a15 p2.5 / a13 p2.6 / a14 p1.0 / t2 p1.1 / t2ex vcc p0.0 / a0 p0.1 / a1 p0.2 / a2 p0.3 / a3 pdil/ 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 cdil40 p1.6/rxd_1 p1.4 p1.2/rxd_1 p3.4/t0 see alternate function on port 1 on page 32 for accurate rxd_1 and txd_1 pin location, depending on auxr register configuration.
6 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 3. pin description for 40/44 pin packages mnemonic pin number type name and function dil lcc vqfp 1.4 v ss 20 22 16 i ground: 0v reference vss1 1 39 i optional ground: contact the sales of?ce for ground connection. v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle and power- down operation p0.0-p0.7 39-32 43-36 37-30 i/o port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them ?oat and can be used as high impedance inputs. port 0 pins must be polarized to vcc or vss in order to prevent any parasitic current consumption. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-up when emitting 1s. port 0 also inputs the code bytes during eprom programming. external pull-ups are required during program veri?cation during which p0 outputs the code bytes. p1.0-p1.7 1-8 2-9 40-44 1-3 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. port 1 also receives the low-order address byte during memory programming and veri?cation. alternate functions for tsc8x54/58 port 1 include: 1 2 40 i/o t2 (p1.0): timer/counter 2 external count input/clockout 2 3 41 i t2ex (p1.1): timer/counter 2 reload/capture/direction control 3 4 7 8 4 5 8 9 42 43 2 3 i o i o depending on values of (m1ua_1, m0ua_1) bits located into auxr register, the uart_1 pins are alternate functins of p1 with two possible locations. first location: p1.2: rxd_1, serial input port for uart_1 p1.3: txd_1, serial output port for uart_1 second location: p1.6: rxd_1, serial input port for uart_1 p1.7: txd_1, serial output port for uart_1 see alternate function on port 1 on page 32 p2.0-p2.7 21-28 24-31 18-25 i/o port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr).in this application, it uses strong internal pull-ups emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 sfr. some port 2 pins receive the high order address bits during eprom programming and veri?cation: p2.0 to p2.5 p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also serves the special features of the 80c51 family, as listed below. 10 11 5 i rxd_0 (p3.0): serial input port for uart_0 11 13 7 o txd_0 (p3.1): serial output port for uart_0 12 14 8 i int0 (p3.2): external interrupt 0 13 15 9 i int1 (p3.3): external interrupt 1 14 16 10 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 16 18 12 o wr (p3.6): external data memory write strobe 17 19 13 o rd (p3.7): external data memory read strobe
rev. d - 15 january, 2001 7 ts80c51u2 ts83c51u2 ts87c51u2 mnemonic pin number type name and function dil lcc vqfp 1.4 reset 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc. if the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated. ale/ pr og 30 33 27 o (i) address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (1/3 in x2 mode) the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input ( pr og) during eprom programming. ale can be disabled by setting sfrs auxr.0 bit. with this bit set, ale will be inactive during internal fetches. psen 29 32 26 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea/v pp 31 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h and 3fffh (rb) or 7fffh (rc), or ffffh (rd). if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 3fffh (rb) or 7fffh (rc) ea must be held low for romless devices. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. if security level 1 is programmed, ea will be internally latched on reset. xtal1 19 21 15 i crystal 1: input to the inverting oscillator ampli?er and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator ampli?er rxd_1 - 12 6 i serial input for uart_1. for 44-pin package only. txd_1 - 34 28 o serial ouput for uart_1. this pin is pulled up by a 100k resistor when not selected. for 44-pin package only. table 3. pin description for 40/44 pin packages
8 rev. d - 06 december, 2000 ts87c51u2 7. ts80c51u2 enhanced features in comparison to the original 80c52, the ts80c51u2 implements some new features, which are : the x2 option. the second full duplex enhanced uart. the baud rate generator. the dual data pointer. the watchdog. the 4 level interrupt priority system. the power-off flag. the once mode. the ale disabling. some enhanced features are also located in the uarts and the timer 2. 7.1 x2 feature the ts80c51u2 core needs only 6 clock periods per machine cycle. this feature called x2 provides the following advantages: l divide frequency crystals by 2 (cheaper crystals) while keeping same cpu power. l save power consumption while keeping same cpu power (oscillator power saving). l save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. l increase cpu power by 2 while keeping same crystal frequency. in order to keep the original c51 compatibility, a divider by 2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by software. 7.1.1 description the clock for the whole circuit and peripheral is first divided by two before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 1. shows the clock generation block diagram. x2 bit is validated on xtal1 ? 2 rising edge to avoid glitches when switching from x2 to std mode. figure 2. shows the mode switching waveforms. figure 1. clock generation diagram xtal1 2 ckcon reg x2 state machine: 6 clock cycles. cpu control f osc f xtal 0 1 xtal1:2
rev. d - 06 december, 2000 9 ts87c51u2 figure 2. mode switching waveforms the x2 bit in the ckcon register (see table 4.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. at reset, the standard speed is activated (std mode). setting this bit activates the x2 feature (x2 mode). caution in order to prevent any incorrect operation while operating in x2 mode, user must be aware that all peripherals using clock frequency as time reference (uarts, timers) will have their time reference divided by two. for example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. uart with 4800 baud rate will have 9600 baud rate. xtal1:2 xtal1 cpu clock x2 bit x2 mode std mode std mode
10 rev. d - 06 december, 2000 ts87c51u2 table 4. ckcon register ckcon - clock control register (8fh) reset value = xxxx xxx0b not bit addressable for further details on the x2 feature, please refer to anm072 available on the web (http://www.atmel-wm.com) 7 6 5 4 3 2 1 0 - - - - - - - x2 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 x2 cpu and peripheral clock bit clear to select 12 clock periods per machine cycle (std mode, f osc =f xtal / 2). set to select 6 clock periods per machine cycle (x2 mode, f osc =f xtal ).
rev. d - 15 january, 2001 11 ts80c51u2 ts83c51u2 ts87c51u2 7.2 dual data pointer register ddptr the additional data pointer can be used to speed up code execution and reduce code size in a number of ways. the dual dptr structure is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 (see table 5.) that allows the program code to switch between them (refer to figure 3). figure 3. use of dual pointer external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1
12 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 5. auxr1: auxiliary register 1 reset value = xxxx xxx0 not bit addressable user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new feature. in that case, the reset value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a source pointer and the other one as a "destination" pointer. 7 6 5 4 3 2 1 0 - - - - - - - dps bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 dps data pointer selection clear to select dptr0. set to select dptr1.
rev. d - 15 january, 2001 13 ts80c51u2 ts83c51u2 ts87c51u2 assembly language ; block move using dual data pointers ; destroys dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6 jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruction (inc auxr1), the routine will exit with dps in the opposite state.
14 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 7.3 timer 2 the timer 2 in the ts80c51u2 is compatible with the timer 2 in the 80c52. it is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, th2 and tl2, connected in cascade. it is controlled by t2con register (see table 6) and t2mod register (see table 7). timer 2 operation is similar to timer 0 and timer 1. c/ t2 selects f osc /12 (timer operation) or external pin t2 (counter operation) as the timer clock input. setting tr2 allows tl2 to be incremented by the selected input. timer 2 has 3 operating modes: capture, autoreload and baud rate generator. these modes are selected by the combination of rclk, tclk and cp/ rl2 (t2con), as described in the atmel wireless & microcontrollers 8- bit microcontroller hardware description. refer to the atmel wireless & microcontrollers 8-bit microcontroller hardware description for the description of capture and baud rate generator modes. in ts80c51u2 timer 2 includes the following enhancements: l auto-reload mode with up or down counter l programmable clock-output 7.3.1 auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. if dcen bit in t2mod is cleared, timer 2 behaves as in 80c52 (refer to the atmel wireless & microcontrollers 8-bit microcontroller hardware description). if dcen bit is set, timer 2 acts as an up/down timer/counter as shown in figure 4. in this mode the t2ex pin controls the direction of count. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the underflow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. exf2 does not generate any interrupt. this bit can be used to provide 17-bit resolution.
rev. d - 15 january, 2001 15 ts80c51u2 ts83c51u2 ts87c51u2 figure 4. auto-reload mode up/down counter (dcen = 1) 7.3.2 programmable clock-output in the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (see figure 5) . the input clock increments tl2 at frequency f osc /2. the timer repeatedly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers: for a 16 mhz system clock, timer 2 has a programmable frequency range of 61 hz (f osc /2 16) to 4 mhz (f osc /4). the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: l set t2oe bit in t2mod register. l clear c/ t2 bit in t2con register. l determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. l enter a 16-bit initial value in timer registers th2/tl2. it can be the same as the reload value or a different one depending on the application. (down counting reload value) c/ t2 tf2 tr2 t2 exf2 th2 (8-bit) tl2 (8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt xtal1 : 12 f osc f xtal 0 1 t2conreg t2conreg t2conreg t2conreg t2ex: if dcen=1, 1=up if dcen=1, 0=down if dcen = 0, up counting (:6 in x2 mode) clock outfrequency C f osc 4 65536 rcap 2 h C rcap 2 l () -------------------------------------------------------------------------------------- =
16 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 l to start the timer, set tr2 run control bit in t2con register. it is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. for this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the rcap2h and rcap2l registers. figure 5. clock-out mode c/ t2=0 :2 exf2 tr2 overflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 xtal1 t2con reg t2con reg t2con reg t2mod reg interrupt qd toggle exen2 (:1 in x2 mode)
rev. d - 15 january, 2001 17 ts80c51u2 ts83c51u2 ts87c51u2 table 6. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 over?ow flag must be cleared by software. set by hardware on timer 2 over?ow, if rclk = 0 and tclk = 0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. when set, causes the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesnt cause an interrupt in up/down counter mode (dcen = 1) 5 rclk_0 receive clock bit for uart_0 clear to use timer 1 over?ow as receive clock for serial port in mode 1 or 3. set to use timer 2 over?ow as receive clock for serial port in mode 1 or 3. 4 tclk_0 transmit clock bit for uart_0 clear to use timer 1 over?ow as transmit clock for serial port in mode 1 or 3. set to use timer 2 over?ow as transmit clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2 tr2 timer 2 run control bit clear to turn off timer 2. set to turn on timer 2. 1 c/t2# timer/counter 2 select bit clear for timer operation (input from internal clock system: f osc ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 over?ow. clear to auto-reload on timer 2 over?ows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1.
18 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 7. t2mod register t2mod - timer 2 mode control register (c9h) reset value = xxxx xx00b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - t2oe dcen bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 t2oe timer 2 output enable bit clear to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit clear to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter.
rev. d - 15 january, 2001 19 ts80c51u2 ts83c51u2 ts87c51u2 7.4 ts80c51u2 serial i/o ports enhancements the serial i/o ports in the ts80c51u2 are compatible with the serial i/o port in the 80c52. they provide both synchronous and asynchronous communication modes. they operate as universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o ports include the following enhancements: l framing error detection l automatic address recognition as these improvements apply to both uart, most of the time in the following lines, there wont be any reference to uart_0 or uart_1, but only to uart, generally speaking. idem for the bits in registers. 7.4.1 framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 6). figure 6. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 8.) bit is set. ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0_0 smod1_0 to uart framing error control sm0 to uart mode control (smod0_0 = 0 for uart_0) set fe bit if stop bit is 0 (framing error) (smod0_0 = 1 for uart_0) scon_0 for uart_0 (98h) (scon_1 for uart_1 (c0h)) pcon for uart_0 (87h) (smod bits for uart_1 are located in bdrcon_1)
20 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 7. and figure 8.). figure 7. uart timings in mode 1 figure 8. uart timings in modes 2 and 3 7.4.2 automatic address recognition the automatic address recognition feature is enabled for each uart when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the devices address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). 7.4.3 given address each uart has an individual address that is specified in saddr_0 or saddr_1 register; the saden_0 or saden_1 register is a mask byte that contains dont-care bits (defined by zeros) to form the devices given address. the dont-care bits provide the flexibility to address one or more slaves at a time. the following example data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1 ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1
rev. d - 15 january, 2001 21 ts80c51u2 ts83c51u2 ts87c51u2 illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr 0101 0110b saden 1111 1100b given 0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a: saddr 1111 0001b saden 1111 1010b given 1111 0x0xb slave b: saddr 1111 0011b saden 1111 1001b given 1111 0xx1b slave c: saddr 1111 0010b saden 1111 1101b given 1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a dont-care bit; for slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a dont care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 7.4.4 broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as dont-care bits, e.g.: saddr 0101 0110b saden 1111 1100b broadcast =saddr or saden 1111 111xb the use of dont-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a: saddr 1111 0001b saden 1111 1010b broadcast 1111 1x11b, slave b: saddr 1111 0011b saden 1111 1001b broadcast 1111 1x11b, slave c: saddr= 1111 0010b saden 1111 1101b broadcast 1111 1111b for slaves a and b, bit 2 is a dont care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. 7.4.5 reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all dont-care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition.
22 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 7.4.6 baud rate selection for uart0_0 for mode 1 and 3 the baud rate generator for transmit and receive clocks can be selected separately via the t2con and bdrcon registers. figure 9. baud rate selection 7.4.7 baud rate selection for uart1_1 for mode 1 and 3 the baud rate generator for transmit and receive clocks can be selected separately via the bdrcon_1 register. figure 10. baud rate selection rclk_0 / 16 rbck_0 int_brg_0 0 1 timer1_brg 0 1 0 1 timer2_brg tclk_0 tbck_0 int_brg_0 timer1_brg timer2_brg timer_brg rx_0 clock / 16 0 1 timer_brg tx_0 clock 0 1 tclk_1 tbck_1 int_brg_1 timer1_brg timer2_brg / 16 0 1 timer_brg tx_1 clock rclk_1 / 16 rbck_1 int_brg_1 0 1 timer1_brg 0 1 timer2_brg timer_brg rx_1 clock
rev. d - 15 january, 2001 23 ts80c51u2 ts83c51u2 ts87c51u2 7.4.8 baud rate selection table for uart_0 7.4.9 baud rate selection table for uart_1 7.4.10 internal baud rate generator (brg) when the internal baud rate generator is used, the baud rates are determined by the brg over?ow depending on the brl reload value, the x2 bit in ckon register, the value of spd bit (speed mode) in bdrcon register and the value of the smod1_0 bit in pcon register (for uart_0) or smod1_1 in bdrcon_1 register (for uart_1). the internal baud rate generator is common to both uarts: figure 11. internal baud rate tclk_0 rclk_0 tbck_0 rbck_0 clock source for uart_0 tx clock source uart_0 rx 0 0 0 0 timer 1 timer 1 1 0 0 0 timer 2 timer 1 0 1 0 0 timer 1 timer 2 1 1 0 0 timer 2 timer 2 x 0 1 0 int_brg_0 timer 1 x 1 1 0 int_brg_0 timer 2 0 x 0 1 timer 1 int_brg_0 1 x 0 1 timer 2 int_brg_0 x x 1 1 int_brg_0 int_brg_0 tclk_1 rclk_1 tbck_1 rbck_1 clock source for uart_1 tx clock source uart_1 rx 0 0 0 0 timer 1 timer 1 1 0 0 0 timer 2 timer 1 0 1 0 0 timer 1 timer 2 1 1 0 0 timer 2 timer 2 x 0 1 0 int_brg_1 timer 1 x 1 1 0 int_brg_1 timer 2 0 x 0 1 timer 1 int_brg_1 1 x 0 1 timer 2 int_brg_1 x x 1 1 int_brg_1 int_brg_1 xtal1 /2 brg f xtal 0 1 0 1 /6 brl /2 0 1 /2 0 1 int_brg_0 int_brg_1 x2 spd brr smod1_1 smod1_0 auto reload counter over?ow
24 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 l for uart_1 l for uart_0 example of computed value when x2=1, smod1=1, spd=1 example of computed value when x2=0, smod1=0, spd=0 the baud rate generator can be used for mode 1 or 3 (refer to figures 9 and 10), but also for mode 0 for both uarts, thanks to the bit src located in bdrcon register (table 12) baud rates f xtal = 16.384 mhz f xtal = 24mhz brl error (%) brl error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - baud rates f osc = 16.384 mhz f osc = 24mhz brl error (%) brl error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 baud_rate = 2 smod1_1 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x [256 - (brl)] (brl) = 256 - 2 smod1_1 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x baud_rate baud_rate = 2 smod1_0 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x [256 - (brl)] (brl) = 256 - 2 smod1_0 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x baud_rate
rev. d - 15 january, 2001 25 ts80c51u2 ts83c51u2 ts87c51u2 7.5 uarts registers saden_0 - slave address mask register for uart_0 (b9h) reset value = 0000 0000b saden_1 - slave address mask register for uart_1 (bah) reset value = 0000 0000b saddr_0 - slave address register for uart_0 (a9h) reset value = 0000 0000b saddr_1 - slave address register for uart_1 (aah) reset value = 0000 0000b sbuf_0 - serial buffer register for uart_0 (99h) reset value = xxxx xxxxb sbuf_1 - serial buffer register for uart_1 (c1h) reset value = xxxx xxxxb brl - baud rate reload register for the internal baud rate generator, uart_0 and uart_1 (9ah) reset value = 0000 0000b 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
26 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 8. scon register scon_0 - serial control register for uart_0 (98h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 fe_0/ sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 bit number bit mnemonic description 7 fe_0 framing error bit (smod0_0=1) for uart_0 clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0_0 must be set to enable access to the fe bit sm0_0 serial port mode bit 0 (smod0_0=0) for uart_0 refer to sm1 for serial port mode selection. smod0_0 must be cleared to enable access to the sm0_0 bit 6 sm1_0 serial port mode bit 1 for uart_0 sm0_0 sm1_0 mode description baud rate 0 0 0 shift register f xtal /12 (f xtal /6 x2 mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f xtal /64 or f xtal /32 (f xtal /32 or f xtal /16 x2 mode) 1 1 3 9-bit uart variable 5 sm2_0 serial port mode 2 bit / multiprocessor communication enable bit for uart_0 clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4 ren_0 reception enable bit for uart_0 clear to disable serial reception. set to enable serial reception. 3 tb8_0 transmitter bit 8 / ninth bit to transmit in modes 2 and 3 for uart_0. clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8_0 receiver bit 8 / ninth bit received in modes 2 and 3 for uart_0 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1 ti_0 transmit interrupt ?ag for uart_0 clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 ri_0 receive interrupt ?ag for uart_0 clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 7. and figure 8. in the other modes.
rev. d - 15 january, 2001 27 ts80c51u2 ts83c51u2 ts87c51u2 table 9. scon register scon_1 - serial control register for uart_1 (c0h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 fe_1/ sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 bit number bit mnemonic description 7 fe_1 framing error bit (smod0_1=1) for uart_1 clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0_1 must be set to enable access to the fe bit sm0_1 serial port mode bit 0 (smod0_1=0) for uart_1 refer to sm1 for serial port mode selection. smod0_1 must be cleared to enable access to the sm0_1 bit 6 sm1_1 serial port mode bit 1 for uart_1 sm0_1 sm1_1 mode description baud rate 0 0 0 shift register f xtal /12 (f xtal /6 x2 mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f xtal /64 or f xtal /32 (f xtal /32 or f xtal /16 x2 mode) 1 1 3 9-bit uart variable 5 sm2_1 serial port mode 2 bit / multiprocessor communication enable bit for uart_1 clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4 ren_1 reception enable bit for uart_1 clear to disable serial reception. set to enable serial reception. 3 tb8_1 transmitter bit 8 / ninth bit to transmit in modes 2 and 3 for uart_1. clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8_1 receiver bit 8 / ninth bit received in modes 2 and 3 for uart_1 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1 ti_1 transmit interrupt ?ag for uart_1 clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 ri_1 receive interrupt ?ag for uart_1 clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 7. and figure 8. in the other modes.
28 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 10. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 over?ow flag must be cleared by software. set by hardware on timer 2 over?ow, if rclk = 0 and tclk = 0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. when set, causes the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesnt cause an interrupt in up/down counter mode (dcen = 1) 5 rclk_0 receive clock bit for uart_0 clear to use timer 1 over?ow as receive clock for serial port in mode 1 or 3. set to use timer 2 over?ow as receive clock for serial port in mode 1 or 3. 4 tclk_0 transmit clock bit for uart_0 clear to use timer 1 over?ow as transmit clock for serial port in mode 1 or 3. set to use timer 2 over?ow as transmit clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2 tr2 timer 2 run control bit clear to turn off timer 2. set to turn on timer 2. 1 c/t2# timer/counter 2 select bit clear for timer operation (input from internal clock system: f osc ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 over?ow. clear to auto-reload on timer 2 over?ows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1.
rev. d - 15 january, 2001 29 ts80c51u2 ts83c51u2 ts87c51u2 table 11. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesnt affect the value of this bit. 7 6 5 4 3 2 1 0 smod1_0 smod0_0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1_0 serial port mode bit 1 for uart_0 set to select double baud rate in mode 1, 2 or 3. 6 smod0_0 serial port mode bit 0 for uart_0 clear to select sm0_0 bit in scon_0 register. set to to select fe_0 bit in scon_0 register. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 pof power-off flag clear to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3 gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2 gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
30 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 12. bdrcon register bdrcon - baud rate control register (9bh) reset value = xxx0 0000b 7 6 5 4 3 2 1 0 - - - brr tbck_0 rbck_0 spd src bit number bit mne- monic description 7 - reserved the value read from this bit is indeterminate. do not set this bit 6 - reserved the value read from this bit is indeterminate. do not set this bit 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 brr baud rate run control bit clear to stop the internal baud rate generator. set to start the internal baud rate generator. 3 tbck_0 transmission baud rate generator selection bit for uart_0 clear to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 2 rbck_0 reception baud rate generator selection bit for uart_0 clear to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 1 spd baud rate speed control bit for uart_0 clear to select the slow baud rate generator. set to select the fast baud rate generator. 0 src baud rate source select bit in mode 0 for uart_0 and uart_1 clear to select f osc /12 as the baud rate generator (f osc /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0..
rev. d - 15 january, 2001 31 ts80c51u2 ts83c51u2 ts87c51u2 table 13. bdrcon_1 register bdrcon_1 - baud rate control register for uart_1 (9ch) reset value = 0000 00xxb 7 6 5 4 3 2 1 0 smod1_1 smod0_1 rclk_1 tclk_1 tbck_1 rbck_1 - - bit number bit mne- monic description 7 smod1_1 serial port mode bit 1 for uart_1 set to select double baud rate, in mode 1, 2 and 3. 6 smod0_1 scon select bit for uart_1 clear to select sm0_1 bit in scon_1 register.. set to to select fe_1 bit in scon_1 register. 5 rclk_1 receive clock bit for uart_1 clear to select timer 1 as receive baud rate generator for the uart_1 set to select timer 2 as the receive baud rate generator for the uart_1 4 tclk_1 transmit clock bit for uart_1 clear to select timer 1 as transmit baud rate generator for the uart_1 set to select timer 2 as the transmit baud rate generator for the uart_1. 3 tbck_1 transmission baud rate generator selection bit for uart_1 clear to select timer 1 or timer 2 for the baud rate generator, for tx. set to select internal baud rate generator for tx. 2 rbck_1 reception baud rate generator selection bit for uart_1 clear to select timer 1 or timer 2 for the baud rate generator for rx. set to select internal baud rate generator for rx. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 - reserved the value read from this bit is indeterminate. do not set this bit.
32 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 7.6 alternate function on port 1 the m1ua_1 and m0ua_1 bits located into auxr register at bit location 7 and 6 permit to validate alternate functions located on port 1. following the combination of these two bits, the txd_1 output and rxd_1 input of uart_1 take place on port 1 pins (two different locations are possible) and the other locations of txd_1 and rxd_1 available only for 44-pin package are no more valid. table 14. auxr register auxr - auxiliary register (8eh) reset value = 00xx xxx0b not bit addressable 7 6 5 4 3 2 1 0 m1ua_1 m0ua_1 - - - - - ao bit number bit mne- monic description 7 m1ua_1 multiplex i/os of uart_1 bit 1 this bit is used in conjunction with m0ua_1 bit to specify where are multiplexed uart_1 pins. 6 m0ua_1 multiplex i/os of uart_1 bit 0 this bit is used in conjunction with m1ua_1 bit bit to specify where are multiplexed uart_1 pins. m1u a_1 m0u a_1 result 0 0 uart_1 pins are disabled. 0 1 uart_1 pins are located on pins (6, 28) or (12, 34) for 44-package only. 1 0 uart_1 pins are alternate functions of p1 located at p1.2 and p1.3. 1 1 uart_1 pins are alternate functions of p1 located at p1.6 and p1.7. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 ao ale output bit clear to restore ale operation during internal fetches. set to disable ale operation during internal fetches.
rev. d - 15 january, 2001 33 ts80c51u2 ts83c51u2 ts87c51u2 7.7 interrupt system the ts80c51u2 has a total of 7 interrupt vectors: two external interrupts ( int0 and int1), three timer interrupts (timers 0, 1 and 2) and the two serial port interrupts. these interrupts are shown in figure 12. figure 12. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (see table 16.). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the interrupt priority register (see table 17.) and in the interrupt priority high register (see table 18.). shows the bit values and priority levels associated with each combination. the second uart interrupt vector is located at address 0033h. all other vector addresses are the same as standard c52 devices. ie1 0 3 high priority interrupt interrupt polling sequence, decreasing from high to low priority low priority interrupt global disable individual enable exf2 tf2 ti_0 ri_0 tf0 int0 int1 tf1 iph, ip ie0 0 3 0 3 0 3 0 3 0 3 ti_1 ri_1
34 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 15. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cant be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. table 16. ie register ie - interrupt enable register (a8h) reset value = 0000 0000b bit addressable iph.x ip.x interrupt level priority 0 0 0 (lowest) 0 1 1 1 0 2 1 1 3 (highest) 7 6 5 4 3 2 1 0 ea es_1 et2 es_0 et1 ex1 et0 ex0 bit number bit mnemonic description 7 ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 6 es_1 serial port enable bit for uart_1 clear to disable serial port interrupt. set to enable serial port interrupt. 5 et2 timer 2 over?ow interrupt enable bit clear to disable timer 2 over?ow interrupt. set to enable timer 2 over?ow interrupt. 4 es_0 serial port enable bit for uart_0 clear to disable serial port interrupt. set to enable serial port interrupt. 3 et1 timer 1 over?ow interrupt enable bit clear to disable timer 1 over?ow interrupt. set to enable timer 1 over?ow interrupt. 2 ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1 et0 timer 0 over?ow interrupt enable bit clear to disable timer 0 over?ow interrupt. set to enable timer 0 over?ow interrupt. 0 ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
rev. d - 15 january, 2001 35 ts80c51u2 ts83c51u2 ts87c51u2 table 17. ip register ip - interrupt priority register (b8h) reset value = x000 0000b bit addressable 7 6 5 4 3 2 1 0 - ps_1 pt2 ps_0 pt1 px1 pt0 px0 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 ps_1 serial port priority bit for uart_1 refer to psh for priority level. 5 pt2 timer 2 over?ow interrupt priority bit refer to pt2h for priority level. 4 ps_0 serial port priority bit for uart_0 refer to psh for priority level. 3 pt1 timer 1 over?ow interrupt priority bit refer to pt1h for priority level. 2 px1 external interrupt 1 priority bit refer to px1h for priority level. 1 pt0 timer 0 over?ow interrupt priority bit refer to pt0h for priority level. 0 px0 external interrupt 0 priority bit refer to px0h for priority level.
36 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 18. iph register iph - interrupt priority high register (b7h) reset value = x000 0000b not bit addressable 7 6 5 4 3 2 1 0 - psh_1 pt2h psh_0 pt1h px1h pt0h px0h bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 psh_1 serial port priority high bit for uart_1 psh_1 ps_1 priority le v el 0 0 lowest 01 10 1 1 highest 5 pt2h timer 2 over?ow interrupt priority high bit pt2h pt2 priority le v el 0 0 lowest 01 10 1 1 highest 4 psh_0 serial port priority high bit for uart_0 psh_0 ps_0 priority le v el 0 0 lowest 01 10 1 1 highest 3 pt1h timer 1 over?ow interrupt priority high bit pt1h pt1 priority le v el 0 0 lowest 01 10 1 1 highest 2 px1h external interrupt 1 priority high bit px1h px1 priority le v el 0 0 lowest 01 10 1 1 highest 1 pt0h timer 0 over?ow interrupt priority high bit pt0h pt0 priority le v el 0 0 lowest 01 10 1 1 highest 0 px0h external interrupt 0 priority high bit px0h px0 priority le v el 0 0 lowest 01 10 1 1 highest
rev. d - 15 january, 2001 37 ts80c51u2 ts83c51u2 ts87c51u2 7.8 idle mode an instruction that sets pcon.0 causes that to be the last instruction executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirely : the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occured during normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 7.9 power-down mode to save maximum power, a power-down mode can be invoked by software (refer to 7.4.6, pcon register). in power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power-down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only external interrupts int0 and int1 are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 13. when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. in this case the higher priority interrupt service routine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put ts80c51u2 into power-down mode. figure 13. power-down exit waveform exit from power-down by reset redefines all the sfrs, exit from power-down by external interrupt does no affect the sfrs. exit from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase
38 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 19. the state of ports during idle and power-down modes * port 0 can force a "zero" level. a "one" level will leave port ?oating. mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 port data* port data port data port data idle external 1 1 floating port data address port data power down internal 0 0 port data* port data port data port data power down external 0 0 floating port data port data port data
rev. d - 15 january, 2001 39 ts80c51u2 ts83c51u2 ts87c51u2 7.10 hardware watchdog timer the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from exiting reset. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will drive an output reset high pulse at the rst-pin. 7.10.1 using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, the user needs to service it by writing to 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh) and this will reset the device. when wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycle. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst-pin. the reset pulse duration is 96 x t osc , where t osc = 1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to extend the time-out capability, ranking from 16ms to 2s @ f osc = 12mhz. to manage this feature, refer to wdtprg register description, table 21. (sfr0a7h). table 20. wdtrst register wdtrst address (0a6h) write only, this sfr is used to reset/enable the wdt by writing 01eh then 0e1h in sequence. 7 6 5 4 3 2 1 reset value x x x x x x x
40 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 21. wdtprg register wdtprg address (0a7h) reset value xxxx x000 7.10.2 wdt during power down and idle in power down mode the oscillator stops, which means the wdt also stops. while in power down mode the user does not need to service the wdt. there are 2 methods of exiting power down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power down mode. when power down is exited with hardware reset, servicing the wdt should occur as it normally should whenever the ts80c51u2 is reset. exiting power down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service routine. to ensure that the wdt does not overflow within a few states of exiting of powerdown, it is best to reset the wdt just before entering powerdown. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting the ts80c51u2 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. 7 6 5 4 3 2 1 0 t4 t3 t2 t1 t0 s2 s1 s0 bit number bit mnemonic description 7 t4 reserved do not try to set or clear this bit. 6 t3 5 t2 4 t1 3 t0 2 s2 wdt time-out select bit 2 1 s1 wdt time-out select bit 1 0 s0 wdt time-out select bit 0 s2 s1 s0 selected t ime-out 00 0 (2 14 - 1) machine cycles, 16.3 ms @ 12 mhz 00 1 (2 15 - 1) machine cycles, 32.7 ms @ 12 mhz 01 0 (2 16 - 1) machine cycles, 65.5 ms @ 12 mhz 01 1 (2 17 - 1) machine cycles, 131 ms @ 12 mhz 10 0 (2 18 - 1) machine cycles, 262 ms @ 12 mhz 10 1 (2 19 - 1) machine cycles, 542 ms @ 12 mhz 11 0 (2 20 - 1) machine cycles, 1.05 s @ 12 mhz 11 1 (2 21 - 1) machine cycles, 2.09 s @ 12 mhz
rev. d - 15 january, 2001 41 ts80c51u2 ts83c51u2 ts87c51u2 7.11 once tm mode (on chip emulation) the once mode facilitates testing and debugging of systems using ts80c51u2 without removing the circuit from the board. the once mode is invoked by driving certain pins of the ts80c51u2; the following sequence must be exercised: l pull ale low while the device is in reset (rst high) and psen is high. l hold ale low as rst is deactivated. while the ts80c51u2 is in once mode, an emulator or test cpu can be used to drive the circuit table 26. shows the status of the port pins during once mode. normal operation is restored when normal reset is applied. table 22. external pin status during once mode ale psen port 0 port 1 port 2 port 3 xtal1/2 weak pull-up weak pull-up float weak pull-up weak pull-up weak pull-up active
42 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 7.12 power-off flag the power-off flag allows the user to distinguish between a cold start reset and a warm start reset. a cold start reset is the one induced by v cc switch-on. a warm start reset occurs while v cc is still applied to the device and could be generated for example by an exit from power-down. the power-off flag (pof) is located in pcon register (see table 23.). pof is set by hardware when v cc rises from 0 to its nominal voltage. the pof can be set or cleared by software allowing the user to determine the type of reset. the pof value is only relevant with a vcc range from 4.5v to 5.5v. for lower vcc value, reading pof bit will return indeterminate value. table 23. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable 7 6 5 4 3 2 1 0 smod1_0 smod0_0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1_0 serial port mode bit 1 for uart_0 set to select double baud rate in mode 1, 2 or 3. 6 smod0_0 serial port mode bit 0 for uart_0 clear to select sm0_0 bit in scon_0 register. set to to select fe_0 bit in scon_0 register. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 pof power-off flag clear to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3 gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2 gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
rev. d - 15 january, 2001 43 ts80c51u2 ts83c51u2 ts87c51u2 7.13 reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit location 0. as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. table 24. auxr register auxr - auxiliary register (8eh) reset value = 00xx xxx0b not bit addressable 7 6 5 4 3 2 1 0 m1ua_1 m0ua_1 - - - - - ao bit number bit mne- monic description 7 m1ua_1 multiplex i/os of uart_1 bit 1 this bit is used in conjunction with m0ua_1 bit to specify where are multiplexed uart_1 pins. 6 m0ua_1 multiplex i/os of uart_1 bit 0 this bit is used in conjunction with m1ua_1 bit bit to specify where are multiplexed uart_1 pins. m1ua_1m0ua_1result 0 0 uart_1 pins are disabled. 0 1 uart_1 pins are located on pins (6, 28) or (12, 34) for 44-package only. 1 0 uart_1 pins are alternate functions of p1 located at p1.2 and p1.3. 1 1 uart_1 pins are alternate functions of p1 located at p1.6 and p1.7. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 ao ale output bit clear to restore ale operation during internal fetches. set to disable ale operation during internal fetches.
44 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 8. ts80c51u2 rom 8.1 rom structure the ts83c51u2 rom memory is divided in three different arrays: l the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 kbytes. l the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. l the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 8.2 rom lock system the program lock system, when programmed, protects the on-chip program against software piracy. 8.2.1 encryption array within the rom array are 64 bytes of encryption array that are initially unprogrammed (all ffs). every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. this will ensure program protection. 8.2.2 program lock bits the lock bits when programmed according to table 25. will provide different level of protection for the on-chip code and data. u: unprogrammed p: programmed 8.2.3 signature bytes the ts83c51u2 contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in section 10. 8.2.4 verify algorithm refer to 9.3.4 table 25. program lock bits program lock bits protection description securi- ty level lb1 lb2 lb3 1 u u u no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. movc instruction executed from external program memory returns non encrypted data. 2 p u u movc instruction executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset.
rev. d - 15 january, 2001 45 ts80c51u2 ts83c51u2 ts87c51u2 9. ts87c51u2 eprom 9.1 eprom structure the ts87c51u2 eprom is divided in two different arrays: l the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 kbytes. l the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. in addition a third non programmable array is implemented: l the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 9.2 eprom lock system the program lock system, when programmed, protects the on-chip program against software piracy. 9.2.1 encryption array within the eprom array are 64 bytes of encryption array that are initially unprogrammed (all ffs). every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. this will ensure program protection. 9.2.2 program lock bits the three lock bits, when programmed according to table 26., will provide different level of protection for the on-chip code and data. u: unprogrammed, p: programmed warning: security level 2 and 3 should only be programmed after eprom and core verification. table 26. program lock bits program lock bits protection description security level lb1 lb2 lb3 1 u u u no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. movc instruction executed from external program memory returns non encrypted data. 2 p u u movc instruction executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 u p u same as 2, also verify is disabled. 4 u u p same as 3, also external execution is disabled.
46 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 9.2.3 signature bytes the ts87c51u2 contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in section 10. 9.3 eprom programming 9.3.1 set-up modes in order to program and verify the eprom or to read the signature bytes, the ts87c51u2 is placed in specific set-up modes (see figure 14.). control and program signals must be held at the levels indicated in table 27. 9.3.2 definition of terms address lines: p1.0-p1.7, p2.0-p2.5 respectively for a0-a13. data lines: p0.0-p0.7 for d0-d7 control signals: rst, psen, p2.6, p2.7, p3.3, p3.6, p3.7. program signals: ale/ prog, ea/vpp. table 27. eprom set-up modes mode rst psen ale/ pr og ea/ vpp p2.6 p2.7 p3.3 p3.6 p3.7 program code data 1 0 12.75v 0 1 1 1 1 verify code data 1 0 1 1 0 0 1 1 program encryption array address 0-3fh 1 0 12.75v 0 1 1 0 1 read signature bytes 1 0 1 1 0 0 0 0 program lock bit 1 1 0 12.75v 1 1 1 1 1 program lock bit 2 1 0 12.75v 1 1 1 0 0 program lock bit 3 1 0 12.75v 1 0 1 1 0
rev. d - 15 january, 2001 47 ts80c51u2 ts83c51u2 ts87c51u2 figure 14. set-up modes configuration 9.3.3 programming algorithm the improved quick pulse algorithm is based on the quick pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. to program the ts87c51u2 the following sequence must be exercised: l step 1: activate the combination of control signals. l step 2: input the valid address on the address lines. l step 3: input the appropriate data on the data lines. l step 4: raise ea/vpp from vcc to vpp (typical 12.75v). l step 5: pulse ale/ prog once. l step 6: lower ea/vpp from vpp to vcc repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (see figure 15.). 9.3.4 verify algorithm code array verify must be done after each byte or block of bytes is programmed. in either case, a complete verify of the programmed array will ensure reliable programming of the ts87c51u2. p 2.7 is used to enable data output. to verify the ts87c51u2 code the following sequence must be exercised: l step 1: activate the combination of program and control signals. l step 2: input the valid address on the address lines. l step 3: read data on the data lines. repeat step 2 through 3 changing the address for the entire array verification (see figure 15.) the encryption array cannot be directly verified. verification of the encryption array is done by observing that the code array is well encrypted. +5v vcc p0.0-p0.7 p1.0-p1.7 p2.0-p2.5 vss gnd d0-d7 a0-a7 a8-a13 rst ea/vpp ale/ pr og psen p2.6 p2.7 p3.3 p3.7 p3.6 xtal1 4 to 6 mhz control signals* program signals* * see table 31. for proper value on these inputs
48 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 figure 15. programming and verification signals waveform 9.4 eprom erasure (windowed packages only) erasing the eprom erases the code array, the encryption array and the lock bits returning the parts to full functionality. erasure leaves all the eprom cells in a 1s state (ff). 9.4.1 erasure characteristics the recommended erasure procedure is exposure to ultraviolet light (at 2537 ?) to an integrated dose at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. an exposure of 1 hour is recommended with most of standard erasers. erasure of the eprom begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 ?. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. control sig- nals data in ale/ pr og a0-a12 programming cycle 100 m s d0-d7 ea/vpp data out read/verify cycle 12.75v 5v 0v
rev. d - 15 january, 2001 49 ts80c51u2 ts83c51u2 ts87c51u2 10. signature bytes the ts83/87c51u2 has four signature bytes in location 30h, 31h, 60h and 61h. to read these bytes follow the procedure for eprom verify but activate the control lines provided in table 27. for read signature bytes. table 28. shows the content of the signature byte for the ts83/87c51u2. table 28. signature bytes content location contents comment 30h 58h manufacturer code: atmel wireless & microcontrollers 31h 57h family code: c51 x2 60h 2bh product name: ts83c51u2 60h abh product name: ts87c51u2 61h ffh product revision number
50 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 11. electrical characteristics 11.1 absolute maximum ratings (1) ambiant temperature under bias: c = commercial 0 cto70 c i = industrial -40 cto85 c storage temperature -65 cto+150 c voltage on v cc to v ss -0.5vto+7v voltage on v pp to v ss -0.5vto+13v voltage on any pin to v ss -0.5vtov cc + 0.5 v power dissipation 1 w (2) notes 1. s tresses at or above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is speci?cation is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package. 11.2 power consumption measurement since the introduction of the first c51 devices, every manufacturer made operating icc measurements under reset, which made sense for the designs were the cpu was running under reset. in atmel wireless & microcontrollers new devices, the cpu is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. thats why, while keeping measurements under reset, atmel wireless & microcontrollers presents a new way to measure the operating icc: using an internal test rom, the following code is executed: label: sjmp label (80 fe) ports 1, 2, 3 are disconnected, port 0 is tied to ffh, ea = vcc, rst = vss, xtal2 is not connected and xtal1 is driven by the clock. this is much more representative of the real operating icc.
rev. d - 15 january, 2001 51 ts80c51u2 ts83c51u2 ts87c51u2 11.3 dc parameters for standard voltage t a =0 cto+70 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. t a = -40 cto+85 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. table 29. dc parameters in standard voltage symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 (6) 0.3 0.45 1.0 v v v i ol = 100 m a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) v ol1 output low voltage, port 0 (6) 0.3 0.45 1.0 v v v i ol = 200 m a (4) i ol = 3.2 ma (4) i ol = 7.0 ma (4) v ol2 output low voltage, ale, psen 0.3 0.45 1.0 v v v i ol = 100 m a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) v oh output high voltage, ports 1, 2, 3 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 m a i oh = -30 m a i oh = -60 m a v cc = 5 v 10% v oh1 output high voltage, port 0 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -200 m a i oh = -3.2 ma i oh = -7.0 ma v cc = 5 v 10% v oh2 output high voltage,ale, psen v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -100 m a i oh = -1.6 ma i oh = -3.5 ma v cc = 5 v 10% r rst rst pulldown resistor 50 90 (5) 200 k w i il logical 0 input current ports 1, 2 and 3 -50 m a vin = 0.45 v i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 -650 m a vin = 2.0 v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current 20 (5) 50 m a 2.0 v < v cc < 5.5 v (3) i cc under reset power supply current maximum values, x1 mode: (7) 1 + 0.4 freq (mhz) @12mhz 5.8 @16mhz 7.4 ma v cc = 5.5 v (1)
52 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 11.4 dc parameters for low voltage t a =0 cto+70 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. t a = -40 cto+85 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. table 30. dc parameters for low voltage i cc operating power supply current maximum values, x1 mode: (7) 3 + 0.6 freq (mhz) @12mhz 10.2 @16mhz 12.6 ma v cc = 5.5 v (8) i cc idle power supply current maximum values, x1 mode: (7) 0.25+0.3freq (mhz) @12mhz 3.9 @16mhz 5.1 ma v cc = 5.5 v (2) symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 (6) 0.45 v i ol = 0.8 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.45 v i ol = 1.6 ma (4) v oh output high voltage, ports 1, 2, 3 0.9 v cc v i oh = -10 m a v oh1 output high voltage, port 0, ale, psen 0.9 v cc v i oh = -40 m a i il logical 0 input current ports 1, 2 and 3 -50 m a vin = 0.45 v i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 -650 m a vin = 2.0 v r rst rst pulldown resistor 50 90 (5) 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current 20 (5) 10 (5) 50 30 m a v cc = 2.0 v to 5.5 v (3) v cc = 2.0 v to 3.3 v (3) i cc under reset power supply current maximum values, x1 mode: (7) 1 + 0.2 freq (mhz) @12mhz 3.4 @16mhz 4.2 ma v cc = 3.3 v (1) i cc operating power supply current maximum values, x1 mode: (7) 1 + 0.3 freq (mhz) @12mhz 4.6 @16mhz 5.8 ma v cc = 3.3 v (8) symbol parameter min typ max unit test conditions
rev. d - 15 january, 2001 53 ts80c51u2 ts83c51u2 ts87c51u2 notes 1. i cc under reset is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 20.), v il = v ss + 0.5 v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator used.. 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch ,t chcl = 5 ns, v il =v ss + 0.5 v, v ih =v cc - 0.5 v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 18.). 3. power down i cc is measured with all output pins disconnected; ea = v ss , port 0 = v cc ; xtal2 nc.; rst = v ss (see figure 19.). 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacitive loading 100pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. 7. for other values, please contact your sales of?ce. 8. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 20.), v il = v ss + 0.5 v, v ih =v cc - 0.5v; xtal2 n.c.; ea = port 0 = v cc ; rst = v ss . the internal rom runs the code 80 fe (label: sjmp label). i cc would be slightly higher if a crystal oscillator is used. measurements are made with otp products when possible, which is the worst case. figure 16. i cc test condition, under reset i cc idle power supply current maximum values, x1 mode: (7) 0.15 freq (mhz) + 0.2 @12mhz 2 @16mhz 2.6 ma v cc = 3.3 v (2) symbol parameter min typ max unit test conditions ea v cc v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0
54 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 figure 17. operating i cc test condition figure 18. i cc test condition, idle mode figure 19. i cc test condition, power-down mode figure 20. clock signal waveform for i cc tests in active and idle modes ea v cc v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0 reset = vss after a high pulse during at least 24 clock cycles rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal reset = vss after a high pulse during at least 24 clock cycles rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. reset = vss after a high pulse during at least 24 clock cycles v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns.
rev. d - 15 january, 2001 55 ts80c51u2 ts83c51u2 ts87c51u2 11.5 ac parameters 11.5.1 explanation of the ac symbols each timing symbol has 5 characters. the first character is always a t (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a =0to+70 c (commercial temperature range); v ss =0v;v cc =5v 10%; -m and -v ranges. t a = -40 cto+85 c (industrial temperature range); v ss =0v; v cc =5v 10%; -m and -v ranges. t a =0to+70 c (commercial temperature range); v ss =0v;2.7v 56 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 11.5.2 external program memory characteristics table 34. ac parameters for fix clock table 33. symbol description symbol parameter t oscillator clock period t lhll ale pulse width t avll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction floatafter psen t pxav psen to address valid t aviv address to valid instruction in t plaz psen low to address float speed -m 40 mhz -v x2 mode 30 mhz 60 mhz equiv. -v standard mode 40 mhz -l x2 mode 20 mhz 40 mhz equiv. -l standard mode 30 mhz units symbol min max min max min max min max min max t 25 33 25 50 33 ns t lhll 40 25 42 35 52 ns t avll 10 4 12 5 13 ns t llax 10 4 12 5 13 ns t lliv 70 45 78 65 98 ns t llpl 15 9 17 10 18 ns t plph 55 35 60 50 75 ns t pliv 35 25 50 30 55 ns t pxix 0 0 0 0 0 ns t pxiz 18 12 20 10 18 ns t aviv 85 53 95 80 122 ns t plaz 10 10 10 10 10 ns
rev. d - 15 january, 2001 57 ts80c51u2 ts83c51u2 ts87c51u2 table 35. ac parameters for a variable clock: derating formula 11.5.3 external program memory read cycle figure 21. external program memory read cycle symbol type standard clock x2 clock -m -v -l units t lhll min 2 t - x t - x 10 8 15 ns t avll min t - x 0.5 t - x 15 13 20 ns t llax min t - x 0.5 t - x 15 13 20 ns t lliv max 4 t - x 2 t - x 30 22 35 ns t llpl min t - x 0.5 t - x 10 8 15 ns t plph min 3 t - x 1.5 t - x 20 15 25 ns t pliv max 3 t - x 1.5 t - x 40 25 45 ns t pxix min x x 0 0 0 ns t pxiz max t - x 0.5 t - x 7 5 15 ns t aviv max 5 t - x 2.5 t - x 40 30 45 ns t plaz max x x 10 10 10 ns t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8-a15 12 t clcl t aviv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax
58 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 11.5.4 external data memory characteristics table 36. symbol description symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t av dv address to valid data in t llwl ale to wr or rd t avwl address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high
rev. d - 15 january, 2001 59 ts80c51u2 ts83c51u2 ts87c51u2 table 37. ac parameters for a fix clock speed -m 40 mhz -v x2 mode 30 mhz 60 mhz equiv. -v standard mode 40 mhz -l x2 mode 20 mhz 40 mhz equiv. -l standard mode 30 mhz units symbol min max min max min max min max min max t rlrh 130 85 135 125 175 ns t wlwh 130 85 135 125 175 ns t rldv 100 60 102 95 137 ns t rhdx 0 0 0 0 0 ns t rhdz 30 18 35 25 42 ns t lldv 160 98 165 155 222 ns t av dv 165 100 175 160 235 ns t llwl 50 100 30 70 55 95 45 105 70 130 ns t avwl 75 47 80 70 103 ns t qvwx 10 7 15 5 13 ns t qvwh 160 107 165 155 213 ns t whqx 15 9 17 10 18 ns t rlaz 0 0 0 0 0 ns t whlh 10 40 7 27 15 35 5 45 13 53 ns
60 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 38. ac parameters for a variable clock: derating formula 11.5.5 external data memory write cycle figure 22. external data memory write cycle symbol type standard clock x2 clock -m -v -l units t rlrh min 6 t - x 3 t - x 20 15 25 ns t wlwh min 6 t - x 3 t - x 20 15 25 ns t rldv max 5 t - x 2.5 t - x 25 23 30 ns t rhdx min x x 0 0 0 ns t rhdz max 2 t - x t - x 20 15 25 ns t lldv max 8 t - x 4t -x 40 35 45 ns t av dv max 9 t - x 4.5 t - x 60 50 65 ns t llwl min 3 t - x 1.5 t - x 25 20 30 ns t llwl max 3 t + x 1.5 t + x 25 20 30 ns t avwl min 4 t - x 2 t - x 25 20 30 ns t qvwx min t - x 0.5 t - x 15 10 20 ns t qvwh min 7 t - x 3.5 t - x 15 10 20 ns t whqx min t - x 0.5 t - x 10 8 15 ns t rlaz max x x 0 0 0 ns t whlh min t - x 0.5 t - x 15 10 20 ns t whlh max t + x 0.5 t + x 15 10 20 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh
rev. d - 15 january, 2001 61 ts80c51u2 ts83c51u2 ts87c51u2 11.5.6 external data memory read cycle figure 23. external data memory read cycle 11.5.7 serial port timing - shift register mode table 40. ac parameters for a fix clock table 39. symbol description symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid speed -m 40 mhz -v x2 mode 30 mhz 60 mhz equiv. -v standard mode 40 mhz -l x2 mode 20 mhz 40 mhz equiv. -l standard mode 30 mhz units symbol min max min max min max min max min max t xlxl 300 200 300 300 400 ns t qvhx 200 117 200 200 283 ns t xhqx 30 13 30 30 47 ns t xhdx 0 0 0 0 0 ns t xhdv 117 34 117 117 200 ns ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t av dv t llax t rldv
62 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 table 41. ac parameters for a variable clock: derating formula 11.5.8 shift register timing waveforms figure 24. shift register timing waveforms symbol type standard clock x2 clock -m -v -l units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 50 50 ns t xhqx min 2 t - x t - x 20 20 20 ns t xhdx min x x 0 0 0 ns t xhdv max 10 t - x 5 t- x 133 133 133 ns valid valid input data valid valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid valid valid valid
rev. d - 15 january, 2001 63 ts80c51u2 ts83c51u2 ts87c51u2 11.5.9 eprom programming and verification characteristics t a =21 cto27 c; v ss = 0v; v cc =5v 10% while programming. v cc = operating range while verifying 11.5.10 eprom programming and verification waveforms figure 25. eprom programming and verification waveforms table 42. eprom programming parameters symbol parameter min max units v pp programming supply voltage 12.5 13 v i pp programming supply current 75 ma 1/t clcl oscillator frquency 4 6 mhz t av g l address setup to pr og low 48 t clcl t ghax adress hold after pr og 48 t clcl t dvgl data setup to pr og low 48 t clcl t ghdx data hold after pr og 48 t clcl t ehsh (enable) high to v pp 48 t clcl t shgl v pp setup to pr og low 10 m s t ghsl v pp hold after pr og 10 m s t glgh pr og width 90 110 m s t avqv address to valid data 48 t clcl t elqv enable low to data valid 48 t clcl t ehqz data float after enable 0 48 t clcl t ghsl t ehsh ale/prog t av g l t dvgl p0 p1.0-p1.7 p2.0-p2.5 p3.4-p3.5* ea/v pp control signals (enable) address data in v cc v pp v cc t ghax t ghdx t glgh t shgl address data out t avqv t elqv t ehqz programming verification * 8kb: up to p2.4, 16kb: up to p2.5, 32kb: up to p3.4, 64kb: up to p3.5
64 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 11.5.11 external clock drive characteristics (xtal1) 11.5.12 external clock drive waveforms figure 26. external clock drive waveforms 11.5.13 ac testing input/output waveforms figure 27. ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic 1 and 0.45v for a logic 0. timing measurement are made at v ih min for a logic 1 and v il max for a logic 0. 11.5.14 float waveforms figure 28. float waveforms table 43. ac parameters symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5 v 0.45 v 0.7v cc 0.2v cc -0.1 v t chcl t clcx t clcl t clch t chcx 0.45 v v cc -0.5 v 0.2v cc +0.9 0.2v cc -0.1 input/output v ol +0.1 v v oh -0.1 v float v load v load +0.1 v v load -0.1 v
rev. d - 15 january, 2001 65 ts80c51u2 ts83c51u2 ts87c51u2 for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 3 20ma. 11.5.15 clock waveforms valid in normal clock mode. in x2 mode xtal2 signal must be changed to xtal2 divided by two. figure 29. clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. clock xtal2 ale internal state4 state5 state6 state1 state2 state3 state4 state5 extern al pr ogram memor y fetch read cycle write cycle serial por t shift clock por t opera tion psen p0 p2 (ext) rd p0 p2 p0 p2 wr txd (mode 0) rxd sampled rxd sampled p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled mov dest port (p1, p2, p3) (includes int0, int1, to, t1) mov dest p0 old data new data dpl or rt out data out pcl out (even if program memory is internal) pcl out (if program memory is external) indicates dph or p2 sfr to pch transition dpl or rt out float pcl out (if program memory is external) indicates dph or p2 sfr to pch transition indicates address transitions float float float pcl out pcl out pcl out data sampled data sampled data sampled these signals are not activated during the execution of a movx instruction p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2
66 rev. d - 15 january, 2001 ts80c51u2 ts83c51u2 ts87c51u2 12. ordering information table 44. maximum clock frequency code -m -v -l unit standard mode, oscillator frequency standard mode, internal frequency 40 40 40 40 30 30 mhz x2 mode, oscillator frequency x2 mode, internal equivalent frequency 20 40 30 60 20 40 mhz packages: a: pdil 40 b: plcc 44 e: vqfp 44 (1.4mm) j: window cdil 40* k: window cqpj 44* ts -v: vcc: 5v +/- 10% 40 mhz, x1 mode 30 mhz, x2 mode -l: vcc: 2.7 to 5.5 v 30 mhz, x1 mode 20 mhz, x2 mode -e : samples part number ts80c51u2: romless ts83c51u2zzz: 16k rom, zzz is the customer code ts87c51u2: 16k otp eprom i temperature range i: commercial and industrial -40 to 85 o c -v conditioning r: tape & reel d: dry pack b: tape & reel and dry pack r (*) check with atmel wireless & microcontrollers sales of?ce for availability - ceramic parts only for otp (ts87c51u2) ceramic packages (j, k) are available for prototyping, not for volume production. 87c51u2 b
rev. d - 15 january, 2001 67 ts80c51u2 ts83c51u2 ts87c51u2 table 45. possible ordering entries l -ex for samples l tape and reel available for b and e packages l dry pack mandatory for e packages ts80c51u2 romless ts83c51u2zzz 16k rom ts87c51u2 16k otp -via x x x -vib x x x -vie x x x -lia x x x -lib x x x -lie x x x -ea x x -eb x x -ee x x -ej x -ek x

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